On 7/29/11, Koul, Vinod [off-list ref] wrote:

On Fri, 2011-07-29 at 12:05 +0100, Russell King - ARM Linux wrote:

quoted

On Fri, Jul 29, 2011 at 04:19:20PM +0530, Viresh Kumar wrote:

Typically in few dmac IPs i know of:
There is max limitation of what a burst length can be for dma, and what
a max transfer length can be.
The dma will push/pull data into peripheral FIFO based on
max_burst_length parameter (note length in dma terminology is always
items not bytes, and one item is usually defined as
transfer_length/src_width). For a transfer (single block or in
multi-block) the dmac will break the transaction into multiple bursts
and based on max_burst_length it will push/pull data to/from FIFO. Also
matching FIFO thresholds with max_burst_length is also important and can
be tuned based on perf/power requirements.

Sharing my knowledge, hopefully it helps :)

Thanks. It was indeed helpful. :)

--
viresh