From: Khalid Aziz <redacted>
Date: Mon, 7 Mar 2016 14:06:43 -0700
Good questions. Isn't set of valid VAs already constrained by VA_BITS
(set to 44 in arch/sparc/include/asm/processor_64.h)? As I see it we
are already not using the top 4 bits. Please correct me if I am wrong.
Another limiting constraint is the number of address bits coverable by
the 4-level page tables we use. And this is sign extended so we have
a top-half and a bottom-half with a "hole" in the center of the VA
space.
I want some clarification on the top bits during ADI accesses.
If ADI is enabled, then the top bits of the virtual address are
intepreted as tag bits. Once "verified" with the ADI settings, what
happense to these tag bits? Are they dropped from the virtual address
before being passed down the TLB et al. for translations?
If not, then this means you have to map ADI memory to the correct
location so that the tags match up.
And if that's the case, if you really wanted to mix tags within a
single page, you'd have to map that page several times, once for each
and every cacheline granular tag you'd like to use within that page.