Thread (49 messages) 49 messages, 5 authors, 2018-01-28
STALE3059d REVIEWED: 2 (0M)

[PATCH v4 6/9] eal/arm64: define coherent I/O memory barriers

From: Yongseok Koh <hidden>
Date: 2018-01-25 21:03:24
Subsystem: library code, the rest · Maintainers: Andrew Morton, Linus Torvalds

Cc: Thomas Speier <redacted>

Signed-off-by: Yongseok Koh <redacted>
Acked-by: Thomas Speier <redacted>
Acked-by: Jianbo Liu <redacted>
---
 lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 4 ++++
 1 file changed, 4 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index b6bbd0b32..ee0d0d15a 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -36,6 +36,10 @@ extern "C" {
 
 #define rte_io_rmb() rte_rmb()
 
+#define rte_cio_wmb() dmb(oshst)
+
+#define rte_cio_rmb() dmb(oshld)
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.11.0
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