On Tue, Aug 04, 2026 at 12:51:57AM +0800, Chen-Yu Tsai wrote:
On Tue, Aug 4, 2026 at 12:45 AM James Hilliard
[off-list ref] wrote:
quoted
On Mon, Aug 3, 2026 at 7:18 AM Andrew Lunn [off-list ref] wrote:
quoted
quoted
+ ethernet-phy-control {
+ compatible = "x-powers,ac200-ephy-ctl";
+ nvmem-cells = <&ephy_calibration>;
+ nvmem-cell-names = "calibration";
+ phy-mode = "rmii";
+ };
What do you mean by an ethernet PHY control?
I assume this is not an actual Ethernet PHY, but some control logic
around it? Where is the ethernet PHY itself?
Correct, this is not the Ethernet PHY itself. It is the package-specific
sideband control block that must be configured before the normal Clause 22
PHY registers become usable. For AC200, this control block is accessed
through the parent AC200 I2C regmap. For AC300, the equivalent control block
is accessed through a separate non-PHY Clause 22 address.
Basically, all the PHY behavior that is normally configured using strapping
pins on a discrete PHY is done over this I2C channel.
To me this should still be part of the PHY driver, not a separate
driver. The driver drives the hardware, it should drive all of it, all
in one place.
Andrew