[PATCH 19/21] arm64: dts: allwinner: h6: add AC200 EPHY resources
From: James Hilliard <hidden>
Date: 2026-08-03 05:16:13
Also in:
linux-arm-kernel, linux-devicetree, linux-rockchip, linux-sunxi, lkml
Subsystem:
arm/allwinner sunxi soc support, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Torvalds
Add the H6 I2C3 controller and pinmux, the PWM-derived 24 MHz AC200 clock, SID calibration cells, RMII pinmux, and the AC200 MFD and EPHY control nodes. Describe the co-packaged AC200 INTB output on PB20. Keep both reusable AC200 nodes disabled so boards must explicitly enable the parent and its EPHY control function when the companion is present. Signed-off-by: James Hilliard <redacted> --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 72ce1a75647b..55e6e185a4e5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi@@ -17,6 +17,16 @@ / { #address-cells = <1>; #size-cells = <1>; + ac200_pwm_clk: ac200-clock { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + pwms = <&pwm 1 42 0>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>;
@@ -314,6 +324,15 @@ ths_calibration: thermal-sensor-calibration@14 { cpu_speed_grade: cpu-speed-grade@1c { reg = <0x1c 0x4>; }; + + ephy_calibration: ethernet-phy-calibration@2c,0 { + reg = <0x2c 1>; + bits = <0 4>; + }; + + ac200_bandgap: bandgap@30 { + reg = <0x30 2>; + }; }; timer@3009000 {
@@ -368,6 +387,13 @@ ext_rgmii_pins: rgmii-pins { drive-strength = <40>; }; + ext_rmii_pins: rmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", "PA4", + "PA5", "PA6", "PA7", "PA8", "PA9"; + function = "emac"; + drive-strength = <40>; + }; + hdmi_pins: hdmi-pins { pins = "PH8", "PH9", "PH10"; function = "hdmi";
@@ -388,6 +414,12 @@ i2c2_pins: i2c2-pins { function = "i2c2"; }; + i2c3_pins: i2c3-pins { + pins = "PB17", "PB18"; + function = "i2c3"; + bias-pull-up; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
@@ -414,6 +446,11 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; + pwm1_pin: pwm1-pin { + pins = "PB19"; + function = "pwm1"; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC3";
@@ -626,6 +663,42 @@ i2c2: i2c@5002800 { #size-cells = <0>; }; + i2c3: i2c@5002c00 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002c00 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + ac200: mixed-signal@10 { + compatible = "x-powers,ac200"; + reg = <0x10>; + clocks = <&ac200_pwm_clk>; + interrupt-parent = <&pio>; + interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + nvmem-cells = <&ac200_bandgap>; + nvmem-cell-names = "bandgap"; + status = "disabled"; + + ac200_ephy_ctl: ethernet-phy-control { + compatible = "x-powers,ac200-ephy-ctl"; + nvmem-cells = <&ephy_calibration>; + nvmem-cell-names = "calibration"; + phy-mode = "rmii"; + status = "disabled"; + }; + }; + }; + spi0: spi@5010000 { compatible = "allwinner,sun50i-h6-spi", "allwinner,sun8i-h3-spi";
--
2.53.0