On Thu, 29 Jan 2026 at 12:17, Russell King (Oracle)
[off-list ref] wrote:

On Mon, Jan 26, 2026 at 10:21:57AM +0100, Vincent Guittot wrote:

quoted

+/*
+ * Until now, there is no generic way to describe and set PCIe clock mode.
+ * PCIe controller uses the default CRNS = 0 mode.
+ */
+enum pcie_phy_mode {
+     CRNS = 0, /* Common Reference Clock, No Spread Spectrum */
+     CRSS = 1, /* Common Reference Clock, Spread Spectrum */
+     SRNS = 2, /* Separate Reference Clock, No Spread Spectrum */
+     SRIS = 3  /* Separate Reference Clock, Spread Spectrum */
+};

So this is a PCIe thing. If it's part of the driver's API, then it
should be common and not driver-private.

quoted

+static inline bool is_pcie_phy_mode_valid(int mode)
+{
+     switch (mode) {
+     case CRNS:
+     case CRSS:
+     case SRNS:
+     case SRIS:
+             return true;
+     default:
+             return false;
+     }
+}

This checks that the submode is one of the PCIe private modes that this
driver wants to see.

quoted

+
+static int s32g_serdes_phy_set_mode_ext(struct phy *p,
+                                     enum phy_mode mode, int submode)
+{
+     struct s32g_serdes *serdes = phy_get_drvdata(p);
+
+     if (mode == PHY_MODE_PCIE)
+             return -EINVAL;
+
+     if (!is_pcie_phy_mode_valid(submode))
+             return -EINVAL;

This checks for the PCIe submode, but notice the test immediately
above. PCIE mode is being rejected. So, this driver supports
everything else but PCIe.

That doesn't seem right.

It's a mistake

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