Re: [PATCH 1/4] dt-bindings: serdes: s32g: Add NXP serdes subsystem
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
Date: 2026-01-29 12:50:42
Also in:
linux-arm-kernel, linux-devicetree, linux-phy, lkml
On Mon, Jan 26, 2026 at 10:21:56AM +0100, Vincent Guittot wrote:
quoted hunk ↗ jump to hunk
Describe the serdes subsystem available on the S32G platforms. Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> --- .../bindings/phy/nxp,s32g-serdes.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yamldiff --git a/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml b/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml new file mode 100644 index 000000000000..fad34bee2a4f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml@@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nxp,s32g-serdes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2xxx/S32G3xxx SerDes PHY subsystem + +maintainers: + - Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> + +description: | + The SerDes subsystem on S32G SoC Family includes two types of PHYs: + - One PCIe PHY: Supports various PCIe operation modes + - Two Ethernet Physical Coding Sublayer (XPCS) controllers + + SerDes operation mode selects the enabled PHYs and speeds. Clock frequency + must be adapted accordingly. Below table describes all possible operation + modes. + + Mode PCIe XPCS0 XPCS1 PHY clock Description + SGMII SGMII (MHz) + ------------------------------------------------------------------------- + 0 Gen3 N/A N/A 100 Single PCIe + 1 Gen2 1.25Gbps N/A 100 PCIe/SGMII + 2 Gen2 N/A 1.25Gbps 100 PCIe/SGMII + 3 N/A 1.25Gbps 1.25Gbps 100,125 SGMII + 4 N/A 3.125/1.25Gbps 3.125/1.25Gbps 125 SGMII + 5 Gen2 N/A 3.125Gbps 100 PCIe/SGMII
Shouldn't the mode be configured via phy_set_mode_ext()? This identifies whether it is operating as PCIe or for networking and in the case of networking, the PHY interface mode should be passed as the submode. Have a look at include/linux/phy/pcie.h to see the submodes that may be appropriate to pass to phy_set_mode_ext() - but talk to the PHY subsystem maintainers. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!