[PATCH v2 04/15] docs: dma-api: document DMA_ATTR_CPU_CACHE_CLEAN
From: "Michael S. Tsirkin" <mst@redhat.com>
Date: 2026-01-05 08:23:15
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Subsystem:
documentation, the rest · Maintainers:
Jonathan Corbet, Linus Torvalds
Document DMA_ATTR_CPU_CACHE_CLEAN as implemented in the previous patch. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> --- Documentation/core-api/dma-attributes.rst | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
index 0bdc2be65e57..1d7bfad73b1c 100644
--- a/Documentation/core-api/dma-attributes.rst
+++ b/Documentation/core-api/dma-attributes.rst@@ -148,3 +148,12 @@ DMA_ATTR_MMIO is appropriate. For architectures that require cache flushing for DMA coherence DMA_ATTR_MMIO will not perform any cache flushing. The address provided must never be mapped cacheable into the CPU. + +DMA_ATTR_CPU_CACHE_CLEAN +------------------------ + +This attribute indicates the CPU will not dirty any cacheline overlapping this +DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows +multiple small buffers to safely share a cacheline without risk of data +corruption, suppressing DMA debug warnings about overlapping mappings. +All mappings sharing a cacheline should have this attribute.
--
MST