Hi John,

On Mon, 30 Jun 2025 at 18:23, John Madieu [off-list ref] wrote:

quoted

From: Geert Uytterhoeven <geert@linux-m68k.org>
On Thu, 19 Jun 2025 at 10:22, Lad, Prabhakar [off-list ref]
wrote:

quoted

On Thu, Jun 19, 2025 at 5:34 AM John Madieu
[off-list ref] wrote:

quoted

quoted

From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 18 Jun
2025 at 12:04, John Madieu [off-list ref]
wrote:

quoted

quoted

From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun
2025 at 11:02, John Madieu [off-list ref]
wrote:

quoted

Add clock and reset entries for the Gigabit Ethernet
Interfaces (GBETH
0-1) IPs found on the RZ/G3E SoC. This includes various
PLLs, dividers, and mux clocks needed by these two GBETH IPs.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

quoted

--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c

"The clock gating cells require source clocks to operate correctly. If
the source clocks are stopped, these registers cannot be used."

Has this been sorted out yet? I see no change or mention of it in v3.

Yes, it has been sorted out. I mean they operated properly after
all the tests, even after S2R/wakeup test.

While at it, even with OEN patches applied, I could not reproduce
the issue known to V2H. That's why I've asked if you'd prefer
DEF_MOD_EXTERNAL instead of DEF_MOD (which does not work on V2H)
for consistency with RZ/V2H, I can do that as well.

As DEF_MOD_MUX_EXTERNAL() better matches the undelying
hardware, I prefer that.
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds