Hi John,

On Thu, Jun 19, 2025 at 5:34 AM John Madieu
[off-list ref] wrote:

Hi Geert,

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-----Original Message-----
From: Geert Uytterhoeven <geert@linux-m68k.org>
Sent: Wednesday, June 18, 2025 1:02 PM
To: John Madieu <john.madieu.xa@bp.renesas.com>
Subject: Re: [PATCH v2 1/3] clk: renesas: r9a09g047: Add clock and reset
signals for the GBETH IPs

Hi John,

On Wed, 18 Jun 2025 at 12:04, John Madieu [off-list ref]
wrote:

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From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 11 Jun 2025
at 11:02, John Madieu [off-list ref]
wrote:

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Add clock and reset entries for the Gigabit Ethernet Interfaces
(GBETH
0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
dividers, and mux clocks needed by these two GBETH IPs.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

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--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c

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@@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk

r9a09g047_mod_clks[] __initconst = {

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                                                BUS_MSTOP(8,

BIT(4))),

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        DEF_MOD("sdhi_2_aclk",

CLK_PLLDTY_ACPU_DIV4,

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10, 14, 5, 14,

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                                                BUS_MSTOP(8,
BIT(4))),
+       DEF_MOD("gbeth_0_clk_tx_i",

CLK_SMUX2_GBE0_TXCLK,

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11, 8, 5, 24,

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+                                               BUS_MSTOP(8,

BIT(5))),

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+       DEF_MOD("gbeth_0_clk_rx_i",

CLK_SMUX2_GBE0_RXCLK,

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11, 9, 5, 25,

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+                                               BUS_MSTOP(8,

BIT(5))),

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+       DEF_MOD("gbeth_0_clk_tx_180_i",

CLK_SMUX2_GBE0_TXCLK,

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11, 10, 5, 26,

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+                                               BUS_MSTOP(8,

BIT(5))),

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+       DEF_MOD("gbeth_0_clk_rx_180_i",

CLK_SMUX2_GBE0_RXCLK,

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11, 11, 5, 27,

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+                                               BUS_MSTOP(8,

BIT(5))),

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+       DEF_MOD("gbeth_0_aclk_csr_i",           CLK_PLLDTY_DIV8, 11,

12,

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5, 28,

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+                                               BUS_MSTOP(8,

BIT(5))),

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+       DEF_MOD("gbeth_0_aclk_i",               CLK_PLLDTY_DIV8, 11,

13,

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5, 29,

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+                                               BUS_MSTOP(8,

BIT(5))),

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+       DEF_MOD("gbeth_1_clk_tx_i",

CLK_SMUX2_GBE1_TXCLK,

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11, 14, 5, 30,

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+                                               BUS_MSTOP(8,

BIT(6))),

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+       DEF_MOD("gbeth_1_clk_rx_i",

CLK_SMUX2_GBE1_RXCLK,

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11, 15, 5, 31,

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+                                               BUS_MSTOP(8,

BIT(6))),

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+       DEF_MOD("gbeth_1_clk_tx_180_i",

CLK_SMUX2_GBE1_TXCLK,

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12, 0, 6, 0,

scripts/checkpatch.pl says:

    WARNING: please, no space before tabs

Noted.

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+                                               BUS_MSTOP(8,

BIT(6))),

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+       DEF_MOD("gbeth_1_clk_rx_180_i",

CLK_SMUX2_GBE1_RXCLK,

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12, 1, 6, 1,

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+                                               BUS_MSTOP(8,

BIT(6))),

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+       DEF_MOD("gbeth_1_aclk_csr_i",           CLK_PLLDTY_DIV8, 12,

2,

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6, 2,

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+                                               BUS_MSTOP(8,

BIT(6))),

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+       DEF_MOD("gbeth_1_aclk_i",               CLK_PLLDTY_DIV8, 12,

3,

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6, 3,

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+                                               BUS_MSTOP(8,
+ BIT(6))),

Shouldn't all of these use DEF_MOD_MUX_EXTERNAL() instead of
DEF_MOD(), like on RZ/V2H and RZ/V2N?

Do we really need to use DEF_MOD_MUX_EXTERNAL? Unlike for the RZ/V2H,
On G3E, unbind/bind works with DEF_MOD. I can however switch to
DEF_MOD_MUX_EXTERNAL for consistency if required.

Please let me know.

Does that mean the monitor bits on RZ/G3E do reflect the correct state of
external clocks? If yes, then DEF_MOD() is fine.

Gr{oetje,eeting}s,

                        Geert

Checked DEF_MOD() and had expected result. I'll then it and send v3.

Can you please share the devmem logs for external clocks please. I ask
because the HW team mentioned the below information will be added in
the RZ/V2H(P) HW manual. We need to check if below is not needed on
RZ/G3E.

"The clock gating cells require source clocks to operate correctly. If
the source clocks are stopped, these registers cannot be used."

Cheers,
Prabhakar