-----Original Message-----
From: Andrew Lunn [mailto:andrew@lunn.ch]
Sent: 15 August 2023 02:17
To: Sriranjani P <redacted>
Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
pabeni@redhat.com; robh+dt@kernel.org;
krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
richardcochran@gmail.com; alexandre.torgue@foss.st.com;
joabreu@synopsys.com; mcoquelin.stm32@gmail.com;
alim.akhtar@samsung.com; linux-fsd@tesla.com;
pankaj.dubey@samsung.com; swathi.ks@samsung.com;
ravi.patel@samsung.com; netdev@vger.kernel.org;
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-samsung-
soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Chandrasekar R
[off-list ref]; Suresh Siddha [off-list ref]
Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

quoted

+static const int rx_clock_skew_val[] = {0x2, 0x0};

quoted

+static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
+ins_num) {
+	struct device_node *np = pdev->dev.of_node;
+	struct regmap *syscon;
+	unsigned int reg;
+
+	if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
+		syscon = syscon_regmap_lookup_by_phandle_args(np,
+							      "fsd-rx-clock-

skew",

quoted

+							      1, &reg);
+		if (IS_ERR(syscon)) {
+			dev_err(&pdev->dev,
+				"couldn't get the rx-clock-skew syscon!\n");
+			return PTR_ERR(syscon);
+		}
+
+		regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);

Please could you explain what this is doing.

As per customer requirement, we need to provide a delay of 2ns in FSYS in
both TX and RX path and no delay in peric block

       Andrew

Regards,
Swathi