Hi Claudiu,

Thanks for your patch!

On Mon, Nov 20, 2023 at 8:03 AM Claudiu [off-list ref] wrote:

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

RZ/G3S Smarc Module has Ethernet PHYs (KSZ9131) connected to each Ethernet
IP. For this add proper DT bindings to enable the Ethernet communication
though these PHYs.

The interface b/w PHYs and MACs is RGMII. The skew settings were set to
zero as based on phy-mode (rgmii-id) the KSZ9131 driver enables internal
DLL which adds 2ns delay b/w clocks (TX/RX) and data signals.

So shouldn't you just use phy-mode "rgmii" instead?

Different pin settings were applied to TXC, TX_CTL compared with the rest
of the RGMII pins to comply with requirements for these pins imposed by
HW manual of RZ/G3S (see chapters "Ether Ch0 Voltage Mode Control
Register (ETH0_POC)", "Ether Ch1 Voltage Mode Control Register (ETH1_POC)",
for power source selection, "Ether MII/RGMII Mode Control Register
(ETH_MODE)" for output-enable and "Input Enable Control Register (IEN_m)"
for input-enable configurations).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Cfr. my comment on [PATCH 11/14], this looks odd...

Likewise.

+&eth0 {
+       pinctrl-0 = <&eth0_pins>;
+       pinctrl-names = "default";
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       #address-cells = <1>;
+       #size-cells = <0>;

#{address,size}-cells should be in the SoC-specific .dtsi.
Same for eth1.

+       status = "okay";

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds