Thread (53 messages) 53 messages, 6 authors, 2023-12-06

Re: [PATCH 04/14] clk: renesas: r9a08g045-cpg: Add clock and reset support for ETH0 and ETH1

From: claudiu beznea <claudiu.beznea@tuxon.dev>
Date: 2023-12-04 07:34:25
Also in: linux-arm-kernel, linux-clk, linux-devicetree, linux-gpio, linux-renesas-soc, lkml

Hi, Geert,

On 01.12.2023 17:59, Geert Uytterhoeven wrote:
Hi Claudiu,

On Mon, Nov 20, 2023 at 8:01 AM Claudiu [off-list ref] wrote:
quoted
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

RZ/G3S has 2 Gigabit Ethernet interfaces available. Add clock and reset
support for both of them.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
quoted
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -217,6 +219,16 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
                                        MSTOP(PERI_COM, BIT(11))),
        DEF_MOD("sdhi2_aclk",           R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11,
                                        MSTOP(PERI_COM, BIT(11))),
+       DEF_COUPLED("eth0_axi",         R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0,
+                                       MSTOP(PERI_COM, BIT(2))),
+       DEF_COUPLED("eth0_chi",         R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0,
+                                       MSTOP(PERI_COM, BIT(2))),
+       DEF_MOD("eth0_refclk",          R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0),
+       DEF_COUPLED("eth1_axi",         R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1,
+                                       MSTOP(PERI_COM, BIT(3))),
+       DEF_COUPLED("eth1_chi",         R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1,
+                                       MSTOP(PERI_COM, BIT(3))),
+       DEF_MOD("eth1_refclk",          R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0),
        DEF_MOD("scif0_clk_pck",        R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0,
                                        MSTOP(MCPU2, BIT(1))),
        DEF_MOD("gpio_hclk",            R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0),
LGTM, pending the MSTOP() part.

Is the MSTOP() handling needed to function? IIUIC, all modules are
enabled
out of reset.
MSTOP is not needed for Ethernet to work. Indeed, all modules are enabled
out of reset.
If it is not needed, I can take this patch and remove the MSTOP() part.
It's OK for me. Thank you for handling this.

Anyway, let me know if you encounter issues with it so I can resend it.

Thank you,
Claudiu Beznea
Gr{oetje,eeting}s,

                        Geert
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