Hello Andrew,

On Fri, 24 Mar 2023 13:11:07 +0100
Andrew Lunn [off-list ref] wrote:

On Fri, Mar 24, 2023 at 10:36:41AM +0100, Maxime Chevallier wrote:

quoted

When used over SPI, the register addresses needs to be translated,
compared to when used over MMIO. The translation consists in
applying an offset with reg_base, then downshifting the registers
by 2. This actually changes the register stride from 4 to 1.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
 drivers/mfd/ocelot-spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/ocelot-spi.c b/drivers/mfd/ocelot-spi.c
index 2d1349a10ca9..107cda0544aa 100644
--- a/drivers/mfd/ocelot-spi.c
+++ b/drivers/mfd/ocelot-spi.c

@@ -124,7 +124,7 @@ static int ocelot_spi_initialize(struct device

*dev) 
 static const struct regmap_config ocelot_spi_regmap_config = {
 	.reg_bits = 24,
-	.reg_stride = 4,
+	.reg_stride = 1,
 	.reg_shift = REGMAP_DOWNSHIFT(2),
 	.val_bits = 32,  

This does not look like a bisectable change? Or did it never work
before?

Actually this works in all cases because of "regmap: check for alignment
on translated register addresses" in this series. Before this series,
I think using a stride of 1 would have worked too, as any 4-byte-aligned
accesses are also 1-byte aligned.

But that's also why I need review on this, my understanding is that
reg_stride is used just as a check for alignment, and I couldn't test
this ocelot-related patch on the real HW, so please take it with a
grain of salt :(

Thanks,

Maxime

	Andrew