From: Po-Yu Chuang <redacted>
Date: Thu, 24 Feb 2011 15:27:55 +0800
I guess the problem is because a HW restriction that the rx buffer must be
64 bits aligned. Since I cannot make rx buffer starts at offset 2 bytes, the
IP header, TCP header and data are not 4 bytes aligned. The performance
drops drastically.
I cannot believe that after 20 years of commodity ethernet networking
chips were first designed, people are still designing hardware that
doesn't do this right.
Just emit garbage bytes into the sub-word alignment padding if the chip
wants to word align it's DMA writes.
Even the 15 year old Dec Tulip chips do this properly.