RE: [PPC] Boot problems after the pci-v6.18-changes

-----Original Message-----
From: Bjorn Helgaas <helgaas@kernel.org>
Sent: 2025年11月7日 2:25
To: Hongxing Zhu <hongxing.zhu@nxp.com>
Cc: Christian Zigotzky <redacted>; Manivannan Sadhasivam
[off-list ref]; Bjorn Helgaas [off-list ref];
linux-pci@vger.kernel.org; mad skateman [off-list ref];
R.T.Dickinson [off-list ref]; Christian Zigotzky [off-list ref];
linuxppc-dev [off-list ref]; hypexed@yahoo.com.au;
Darren Stevens [off-list ref];
debian-powerpc@lists.debian.org; John Paul Adrian Glaubitz
[off-list ref]; Lukas Wunner [off-list ref];
regressions@lists.linux.dev; luigi burdo [off-list ref]; Al
[off-list ref]; Roland [off-list ref]
Subject: Re: [PPC] Boot problems after the pci-v6.18-changes

On Thu, Nov 06, 2025 at 08:48:16AM +0000, Hongxing Zhu wrote:

quoted

...

quoted

I tested these patches on i.MX95 EVK board with NVME storage device.
Because that i.MX95 PCIe RC failed enter into L2 when one NVME device
is connected to the port if ASPM L1 is enabled in default.

These patches work as expected, the l0s and l1 can be disabled after
adding the following quirk.

"DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_ANY_ID,
quirk_disable_aspm_l0s_l1_cap);"

Thanks for trying this out.

You're welcome.

So if I understand correctly, the i.MX95 Root Port has
PCI_VENDOR_ID_PHILIPS, and if ASPM L1 is enabled on its link, the link
doesn't go to L2 when suspending?  But it *does* go to L2 on suspend if L1
is disabled?

Yes, it is. The VID on i.MX95 PCIe is PCI_VENDOR_ID_PHILIPS.
If the L1 is disabled, the link go to L2 on suspend successfully.
But failed go to L2, if the L1 is enabled.

I wonder if the issue is with the RC or with the NVMe device.  The
comments in dw_pcie_suspend_noirq() and qcom_pcie_suspend_noirq()
make me wonder if there's something weird about NVMe and L2.

The L1 state check in dw_pcie_suspend_noirq() is removed in my local codes and
tests.

I assume you don't want to disable L0s and L1 for *all* devices with
PCI_VENDOR_ID_PHILIPS though.  Aren't there endpoints with that ID that
can use L0s and L1?

Yes it is.

I used do the tests(L2 entry/exit while L1 is enabled) with one Intel 82574L
 NIC after force remove the workaround of e13 errata.

It works as expected in sanity tests at least. When L1 is enabled in default,
the L2 entry/exit is fine on suspend/resume.

And I suppose the best thing would be if we could enable L0s and L1, but
turn them off before suspending?  That would require something different,
like something in imx_pcie_suspend_noirq() or a
DECLARE_PCI_FIXUP_SUSPEND() quirk.

It's a great idea to disable ASPM L0s, L1 even L1SS before suspending. Since
L2/L3 is saving more power consumption than L0s/L1/L1SS anyway. And it can
avoid the problems on some devices when do L0s/L1/L1SS to L2/L3 state
transition.

Best Regards
Richard Zhu