On Tue, Mar 27, 2018 at 9:54 PM, Arnd Bergmann [off-list ref] wrote:

On Tue, Mar 27, 2018 at 8:54 PM, Alexander Duyck
[off-list ref] wrote:

quoted

On Tue, Mar 27, 2018 at 8:10 AM, Will Deacon [off-list ref] wrote=

:

11.10 STORE BUFFER
Intel 64 and IA-32 processors temporarily store each write (store) to
memory in a store buffer. The store buffer
improves processor performance by allowing the processor to continue
executing instructions without having to
wait until a write to memory and/or to a cache is complete. It also
allows writes to be delayed for more efficient use
of memory-access bus cycles.
In general, the existence of the store buffer is transparent to
software, even in systems that use multiple processors.
The processor ensures that write operations are always carried out in
program order. It also insures that the
contents of the store buffer are always drained to memory in the
following situations:
=E2=80=A2 When an exception or interrupt is generated.
=E2=80=A2 (P6 and more recent processor families only) When a serializing
instruction is executed.
=E2=80=A2 When an I/O instruction is executed.

I guess I/O instruction is still ambiguous on x86, it may just refer
to 'inb'/'outb' style instructions rather than 'mov' on a device MMIO
area.

Here's a link to a reply from Linus that I found on this topic:

http://yarchive.net/comp/linux/write_combining.html

      Arnd