Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

=E4=BA=8E 2011=E5=B9=B412=E6=9C=8813=E6=97=A5 05:09, Artem Bityutskiy =E5=
=86=99=E9=81=93:

On Tue, 2011-12-06 at 18:09 -0600, Scott Wood wrote:

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On 12/03/2011 10:31 PM, shuo.liu@freescale.com wrote:

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From: Liu Shuo<redacted>

Freescale FCM controller has a 2K size limitation of buffer RAM. In o=

rder

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to support the Nand flash chip whose page size is larger than 2K byte=

s,

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we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and s=

ave

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them to a large buffer.

Signed-off-by: Liu Shuo<redacted>
---
v3:
     -remove page_size of struct fsl_elbc_mtd.
     -do a oob write by NAND_CMD_RNDIN.

  drivers/mtd/nand/fsl_elbc_nand.c |  243 +++++++++++++++++++++++++++=

+++++++----

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  1 files changed, 218 insertions(+), 25 deletions(-)

What is the plan for bad block marker migration.

I think we can use a special bbt pattern to indicate whether migration=20
has been done.
(we needn't to define another marker)

Do the migration our chip->scan_bbt as follow :

/*
  * this pattern indicate that the bad block information has been migrate=
d,
  * if this isn't found, we do the migration.
  */
static u8 migrated_bbt_pattern[] =3D {'M', 'b', 'b', 't', '0' };

static int fsl_elbc_bbt(struct mtd_info *mtd)
{
         if (!check_migrated_bbt_pattern())
             bad_block_info_migtrate();

          nand_default_bbt(mtd); /* default function in nand_bbt.c */
}

- LiuShuo