Dan Malek wrote:

On Sep 30, 2005, at 9:22 AM, Alex Zeffertt wrote:

quoted

Are there any drawbacks to this approach?

The general system performance is going to suffer,
and if you really have a cache coherency problem
it only solves the write case and not the read case.

The read case seems to be solved by setting the appropriate GBL bits in 
the parameter ram areas, since the buffers work correctly in both 
directions by just setting cache write-through and coherent (coherent 
alone won't help). Still, there must be a correct way of doing this, but 
I think I have already tried modifying every register that sounds 
related. The errata doesn't list anything useful.

Another way of getting around the problem would be to place the buffers 
in a cache-inhibited memory area and have copy-back caches for other 
data. I successfully tried this in another application without Linux.