Dan Malek wrote:

On Sep 27, 2005, at 4:35 PM, Kalle Pokki wrote:

quoted

OK. Then the question really is why isn't the cache controller 
enforcing coherency between the G2_LE core and the CPM.

Is the GBL and DTB set properly in the function code registers
of the SCC parameter ram?

The 60x bus is used, but snooping wasn't enabled before.

However, even after enabling snooping it still doesn't work right. If 
I'm just within my boot loader I still cannot use e.g. the SMC with WIMG 
bits 0010 and the GBL 1. If I set the write-through in WIMG bits as 
1010, it works. The core now sees the RX buffers from the CPM and, of 
course, my TX buffers since they are written to the memory.

I guess Linux remaps the RAM as copy-back. But snooping should work with 
copy-back caches, shouldn't it?