On Thu, 29 Sep 2005 14:24:07 +0200
Kalle Pokki [off-list ref] wrote:

Kalle Pokki wrote:

quoted

I guess Linux remaps the RAM as copy-back. But snooping should
work with copy-back caches, shouldn't it?

Oh, well. The kernel boots just fine if I add

flags |= _PAGE_WRITETHRU | _PAGE_COHERENT;

in setbat() in arch/ppc/mm/ppc_mmu.c. But this should not depend on
this kind of a hack, should it?

I was experiencing a similar problem with the mpc8260sar ATM driver,
and Kalle's hack seems to fix the problem.

On the 8260 ATM SAR you can specify that the CPM asserts the GBL
signal whenever it accesses buffers, BDs, or interrupt queues. This
allows the cache to snoop accesses to these areas and invalidate cache
lines to keep the cache coherent.

However, there seems to be no way of telling the CPM to assert the GBL
signal when it is accessing External Connection Tables, or Second
Level lookup Tables - both of which are also accessed by the core.

Because of this the cache does not know when the CPM is accessing
these areas.

It seems to me that whilst the CPM was designed to be cache coherent
Freescale have overlooked some areas!

Till now I have worked around this problem by calling
dcache_invalidate_range() and dcache_flush_range() before and after
accesses to these areas.  I'm now considering changing to Kalle's way
of doing it.

Are there any drawbacks to this approach?

TIA,

Alex Zeffertt