Thread (48 messages) 48 messages, 6 authors, 2021-10-28
STALE1677d
Revisions (6)
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[PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and name properties

From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2021-10-12 09:06:31
Also in: linux-arm-kernel, linux-devicetree, lkml
Subsystem: open firmware and flattened device tree bindings, pci driver for imx6, pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Zhu, Lucas Stach, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds

i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 2911e565b260..99d9863a69cd 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -128,6 +128,12 @@ properties:
     enum: [1, 2, 3, 4]
     default: 1
 
+  phys:
+    description: Phandle of the Generic PHY to the PCIe PHY.
+
+  phy-names:
+    const: pcie-phy
+
   reset-gpio:
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
-- 
2.25.1


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