On Wed, Jan 13, 2016 at 3:56 PM, Dave Hansen
[off-list ref] wrote:

On 01/13/2016 03:51 PM, Andy Lutomirski wrote:

quoted

On Wed, Jan 13, 2016 at 3:43 PM, Dave Hansen
[off-list ref] wrote:

quoted

On 01/13/2016 03:35 PM, Andy Lutomirski wrote:

quoted

Can anyone here ask a hardware or microcode person what's going on
with CR3 writes possibly being faster than INVPCID?  Is there some
trick to it?

I just went and measured it myself this morning.  "INVPCID Type 3" (all
contexts no global) on a Skylake system was 15% slower than a CR3 write.

Is that in the same ballpark from what you've observed?

It's similar, except that I was comparing "INVPCID Type 1" (single
context no globals) to a CR3 write.

Ahh, because you're using PCID...  That one I saw as being ~1.85x the
number of cycles that a CR3 write was.

I think that settles it, then:

if (static_cpu_has_safe(X86_FEATURE_PCID)) {
  raw_local_irqsave();
  native_write_cr3(native_read_cr3());
  raw_local_irqrestore();
} else {
  native_write_cr3(native_read_cr3());
}

I don't think it's worth hacking more complexity into switch_mm to
make that annoyance go away.

--Andy

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