Thread (41 messages) 41 messages, 9 authors, 2016-09-06

Re: [RFC 09/13] x86/mm: Disable interrupts when flushing the TLB using CR3

From: Dave Hansen <dave.hansen@linux.intel.com>
Date: 2016-01-13 23:56:22
Also in: lkml

On 01/13/2016 03:51 PM, Andy Lutomirski wrote:
On Wed, Jan 13, 2016 at 3:43 PM, Dave Hansen
[off-list ref] wrote:
quoted
On 01/13/2016 03:35 PM, Andy Lutomirski wrote:
quoted
Can anyone here ask a hardware or microcode person what's going on
with CR3 writes possibly being faster than INVPCID?  Is there some
trick to it?
I just went and measured it myself this morning.  "INVPCID Type 3" (all
contexts no global) on a Skylake system was 15% slower than a CR3 write.

Is that in the same ballpark from what you've observed?
It's similar, except that I was comparing "INVPCID Type 1" (single
context no globals) to a CR3 write.
Ahh, because you're using PCID...  That one I saw as being ~1.85x the
number of cycles that a CR3 write was.
Type 2, at least, is dramatically faster than the pair of CR4 writes
it replaces.
Yeah, I saw the same thing.  Type 2 was ~2.4x faster than the CR4 writes.

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