Hello.

On 1/19/2015 3:35 PM, Markos Chandras wrote:

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From: Leonid Yegoshin <redacted>

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MIPS R6 redefines several instructions and reduces the immediate
field to 9-bits so add related macros for the microassembler.

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Signed-off-by: Leonid Yegoshin <redacted>
Signed-off-by: Markos Chandras <redacted>
---
   arch/mips/mm/uasm.c | 13 ++++++++++++-
   1 file changed, 12 insertions(+), 1 deletion(-)

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diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 4adf30284813..6596b6898637 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c

[...]

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@@ -41,6 +42,8 @@ enum fields {
   #define FUNC_SH        0
   #define SET_MASK    0x7
   #define SET_SH        0
+#define SIMM9_SH    7
+#define SIMM9_MASK    0x1ff

   enum opcode {
       insn_invalid,

@@ -116,6 +119,14 @@ static inline u32 build_scimm(u32 arg)
       return (arg & SCIMM_MASK) << SCIMM_SH;
   }

+static inline u32 build_scimm9(s32 arg)
+{
+    WARN((arg > 0x1ff || arg < -0x200),

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    Not 0xFF and -0x100? The values above don't fit into 9 bits...

Hi,

I think 0x1ff and -0x200 fit into 9-bits. Why do you think they don't?

    Because 0x1ff occupies 9 bits already and -0x200 (~0x200 + 1) occupies at 
least 10 bits. I thought that was pretty obvious...

WBR, Sergei