[PATCH v3 4/7] pwm: tegra: Parametrize enable register offset
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: 2026-03-30 08:54:13
Also in:
linux-pwm, linux-tegra, lkml
Subsystem:
pwm subsystem, tegra pwm driver, the rest · Maintainers:
Uwe Kleine-König, Thierry Reding, Linus Torvalds
On Tegra264, the PWM enablement bit is not located at the base address of the PWM controller. Hence, introduce an enablement offset field in the tegra_pwm_soc structure to describe the offset of the register. Co-developed-by: Yi-Wei Wang <redacted> Signed-off-by: Yi-Wei Wang <redacted> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index cf54f75d92a5..22d709986e8c 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c@@ -61,6 +61,7 @@ struct tegra_pwm_soc { unsigned int num_channels; + unsigned int enable_reg; }; struct tegra_pwm_chip {
@@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, err = pm_runtime_resume_and_get(pwmchip_parent(chip)); if (err) return err; - } else + } else if (pc->soc->enable_reg == PWM_CSR_0) { val |= PWM_ENABLE; + } pwm_writel(pwm, PWM_CSR_0, val);
@@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); int rc = 0; u32 val;
@@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (rc) return rc; - val = pwm_readl(pwm, PWM_CSR_0); + + val = pwm_readl(pwm, pc->soc->enable_reg); val |= PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); return 0; } static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); u32 val; - val = pwm_readl(pwm, PWM_CSR_0); + val = pwm_readl(pwm, pc->soc->enable_reg); val &= ~PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); pm_runtime_put_sync(pwmchip_parent(chip)); }
@@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, + .enable_reg = PWM_CSR_0, }; static const struct tegra_pwm_soc tegra186_pwm_soc = { .num_channels = 1, + .enable_reg = PWM_CSR_0, }; static const struct of_device_id tegra_pwm_of_match[] = {
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2.53.0