[PATCH v3 2/7] pwm: tegra: Avoid hard-coded max clock frequency
From: Mikko Perttunen <mperttunen@nvidia.com>
Date: 2026-03-30 08:54:04
Also in:
linux-pwm, linux-tegra, lkml
Subsystem:
pwm subsystem, tegra pwm driver, the rest · Maintainers:
Uwe Kleine-König, Thierry Reding, Linus Torvalds
From: Yi-Wei Wang <redacted> The clock driving the Tegra PWM IP can be sourced from different parent clocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based upon the current parent clock that can be specified via device-tree. After this, the Tegra194 SoC data becomes redundant, so get rid of it. Signed-off-by: Yi-Wei Wang <redacted> Reviewed-by: Thierry Reding <redacted> Co-developed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- drivers/pwm/pwm-tegra.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 172063b51d44..759b98b97b6e 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c@@ -59,9 +59,6 @@ struct tegra_pwm_soc { unsigned int num_channels; - - /* Maximum IP frequency for given SoCs */ - unsigned long max_frequency; }; struct tegra_pwm_chip {
@@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) return ret; /* Set maximum frequency of the IP */ - ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency); + ret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX); if (ret < 0) { dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); goto put_pm;
@@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) /* Set minimum limit of PWM period for the IP */ pc->min_period_ns = - (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1; pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) {
@@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, - .max_frequency = 48000000UL, }; static const struct tegra_pwm_soc tegra186_pwm_soc = { .num_channels = 1, - .max_frequency = 102000000UL, -}; - -static const struct tegra_pwm_soc tegra194_pwm_soc = { - .num_channels = 1, - .max_frequency = 408000000UL, }; static const struct of_device_id tegra_pwm_of_match[] = { { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc }, { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc }, - { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc }, + { .compatible = "nvidia,tegra194-pwm", .data = &tegra186_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
--
2.53.0