[PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains
From: Claudiu <claudiu.beznea@tuxon.dev>
Date: 2024-02-08 12:44:02
Also in:
linux-clk, linux-renesas-soc, linux-riscv, lkml
Subsystem:
common clk framework, renesas clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Geert Uytterhoeven, Linus Torvalds
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Instantiate always-on power domain for R9A07G043 SoC. At the moment, all the IPs are part of this domain. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> --- drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index acfb06cad441..3a7fddd1fa61 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c@@ -358,6 +358,11 @@ static const unsigned int r9a07g043_no_pm_mod_clks[] = { }; #endif +static const struct rzg2l_cpg_pm_domain_init_data r9a07g043_pm_domains[] = { + DEF_PD("always-on", R9A07G043_PD_ALWAYS_ON, 0, 0, + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), +}; + const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Core Clocks */ .core_clks = r9a07g043_core_clks,
@@ -392,5 +397,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ #endif + /* Power domains. */ + .pm_domains = r9a07g043_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a07g043_pm_domains), + .has_clk_mon_regs = true, };
--
2.39.2