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  PCI: imx6: Add IMX8MM support

On Fri, Jul 23, 2021 at 01:49:55PM -0700, Tim Harvey wrote:

Add IMX8MM support to the existing driver which shares most
functionality with the IMX8MM.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

+	case IMX8MM:
+		offset = imx6_pcie_grp_offset(imx6_pcie);
+
+		dev_info(imx6_pcie->pci->dev, "%s REF_CLK is used!.\n",
+				imx6_pcie->ext_osc ? "EXT" : "PLL");
+		if (imx6_pcie->ext_osc) {
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_AUX_EN,
+					IMX8MM_GPR_PCIE_AUX_EN);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_POWER_OFF, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_SSC_EN, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_EXT);
+			udelay(100);
+			/* Do the PHY common block reset */
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_CMN_RST,
+					IMX8MM_GPR_PCIE_CMN_RST);
+			udelay(200);
+		} else {
+			/* Configure the internal PLL as REF clock */
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_AUX_EN,
+					IMX8MM_GPR_PCIE_AUX_EN);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_POWER_OFF, 0);
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_SSC_EN, 0);

Seems like all the above is common to both cases?  If so, it's a shame
to repeat it because it makes it hard to see what's different.

+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_REF_CLK_SEL,
+					IMX8MM_GPR_PCIE_REF_CLK_PLL);
+			udelay(100);
+			/* Configure the PHY */
+			writel(PCIE_PHY_CMN_REG62_PLL_CLK_OUT,
+					imx6_pcie->phy_base + PCIE_PHY_CMN_REG62);
+			writel(PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM,
+					imx6_pcie->phy_base + PCIE_PHY_CMN_REG64);
+			/* Do the PHY common block reset */
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+					IMX8MM_GPR_PCIE_CMN_RST,
+					IMX8MM_GPR_PCIE_CMN_RST);
+			udelay(200);
+		}
+		/*

+		 * In order to pass the compliance tests.
+		 * Configure the TRSV regiser of iMX8MM PCIe PHY.

The "In order to ..." line isn't quite a sentence.  Maybe it should be
joined with the second line?

s/regiser/register/ ?

+		 */
+		writel(PCIE_PHY_TRSV_REG5_GEN1_DEEMP,
+				imx6_pcie->phy_base + PCIE_PHY_TRSV_REG5);

+	/* check for EXT osc */

Since you have a comment here, it would be useful to spell out "osc"
for newbies like me.  I assume it's short for "oscillator"?

+	imx6_pcie->ext_osc = of_property_read_bool(node, "fsl,ext-osc");