Hi Lucas,

On: 21/03/2014 14:31, Lucas wrote:

Subject: Re: [PATCH v4 5/9] dt-bindings: pci: rcar pcie device tree 

bindings

Am Freitag, den 21.03.2014, 14:18 +0000 schrieb
Phil.Edworthy@renesas.com:

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Hi Lucas,

On 21/03/2014 11:24, Lucas wrote:

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Subject: Re: [PATCH v4 5/9] dt-bindings: pci: rcar pcie device tree 

bindings

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Am Freitag, den 21.03.2014, 10:32 +0000 schrieb Phil Edworthy:

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This patch adds the bindings for the rcar PCIE driver. The driver
resides under drivers/pci/host/pcie-rcar.c

Signed-off-by: Phil Edworthy <redacted>

I have one question below. If you can answer this with yes after
thinking again about it, this is:

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

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---
 Documentation/devicetree/bindings/pci/rcar-pci.txt | 40 

++++++++++++++++++++++

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 1 file changed, 40 insertions(+)
 create mode 100644 

Documentation/devicetree/bindings/pci/rcar-pci.txt

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diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/

Documentation/devicetree/bindings/pci/rcar-pci.txt

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new file mode 100644
index 0000000..0e219b0

--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt

@@ -0,0 +1,40 @@
+* Renesas RCar PCIe interface
+
+Required properties:
+- compatible: should contain one of the following
+   "renesas,r8a7779-pcie", "renesas,r8a7790-pcie", 

"renesas,r8a7791-pcie"

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+- reg: base addresses and lengths of the pcie controller.
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+- interrupts: interrupt values for MSI interrupt
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+   to define the mapping of the PCIe interface to interrupt
+   numbers.
+- clocks: from common clock binding: handle to pci clock.
+- clock-names: from common clock binding: should be "pcie"

You really only have one PCIe clock? So the controller is generating 

the

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PCIe bus clock from it's register clock? No need to enable any other
clock for PCIe to work?

Yes, just the one clock. The PCIe bus clock is an external clock 

dedicated 

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to PCIe and SATA, and we have no control over it.

Is this some kind of always-on clock? If not you probably want a
reference to it from the PCIe driver even if it's shared between SATA
and PCIe. After all you don't want to end up unconditionally enabling
this clock from the board or SoC level just to have PCIe working, right?

Ok, I see, I'll need a reference to a board clock, even if it's always on 
for these boards. 

Regards,
Lucas
-- 
Pengutronix e.K.                           | Lucas Stach |
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Thanks
Phil