Hi Lucas,
On 21/03/2014 11:24, Lucas wrote:
Subject: Re: [PATCH v4 5/9] dt-bindings: pci: rcar pcie device tree
bindings
Am Freitag, den 21.03.2014, 10:32 +0000 schrieb Phil Edworthy:
quoted
This patch adds the bindings for the rcar PCIE driver. The driver
resides under drivers/pci/host/pcie-rcar.c
Signed-off-by: Phil Edworthy <redacted>
I have one question below. If you can answer this with yes after
thinking again about it, this is:
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
quoted
---
Documentation/devicetree/bindings/pci/rcar-pci.txt | 40
++++++++++++++++++++++
quoted
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci.txt
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/
Documentation/devicetree/bindings/pci/rcar-pci.txt
quoted
new file mode 100644
index 0000000..0e219b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -0,0 +1,40 @@
+* Renesas RCar PCIe interface
+
+Required properties:
+- compatible: should contain one of the following
+ "renesas,r8a7779-pcie", "renesas,r8a7790-pcie",
"renesas,r8a7791-pcie"
quoted
+- reg: base addresses and lengths of the pcie controller.
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+- interrupts: interrupt values for MSI interrupt
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+ to define the mapping of the PCIe interface to interrupt
+ numbers.
+- clocks: from common clock binding: handle to pci clock.
+- clock-names: from common clock binding: should be "pcie"
You really only have one PCIe clock? So the controller is generating the
PCIe bus clock from it's register clock? No need to enable any other
clock for PCIe to work?
Yes, just the one clock. The PCIe bus clock is an external clock dedicated
to PCIe and SATA, and we have no control over it.
quoted
+
+Example:
+
+SoC specific DT Entry:
+
+ pcie: pcie@0x01000000 {
+ compatible = "renesas,r8a7790-pcie";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ interrupts = <0 116 4>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 116 4>;
+ clocks = <&mstp3_clks R8A7790_CLK_PCIE>;
+ clock-names = "pcie";
+ status = "disabled";
+ };
--
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|
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Thanks
Phil