Hi Shaopeng,

On 16/07/2025 08:31, Shaopeng Tan (Fujitsu) wrote:

quoted

Register and enable error IRQs. All the MPAM error interrupts indicate a
software bug, e.g. out of range partid. If the error interrupt is ever signalled,
attempt to disable MPAM.

Only the irq handler accesses the ESR register, so no locking is needed.
The work to disable MPAM after an error needs to happen at process context,
use a threaded interrupt.

There is no support for percpu threaded interrupts, for now schedule the work
to be done from the irq handler.

Enabling the IRQs in the MSC may involve cross calling to a CPU that can
access the MSC.

quoted

diff --git a/drivers/platform/arm64/mpam/mpam_devices.c

b/drivers/platform/arm64/mpam/mpam_devices.c
index 145535cd4732..af19cc25d16e 100644

--- a/drivers/platform/arm64/mpam/mpam_devices.c
+++ b/drivers/platform/arm64/mpam/mpam_devices.c

quoted

+static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) {
+	u64 reg;
+	u16 partid;
+	u8 errcode, pmg, ris;
+
+	if (WARN_ON_ONCE(!msc) ||
+	    WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(),
+					   &msc->accessibility)))
+		return IRQ_NONE;
+
+	reg = mpam_msc_read_esr(msc);
+
+	errcode = FIELD_GET(MPAMF_ESR_ERRCODE, reg);
+	if (!errcode)
+		return IRQ_NONE;
+
+	/* Clear level triggered irq */
+	mpam_msc_zero_esr(msc);
+
+	partid = FIELD_GET(MPAMF_ESR_PARTID_OR_MON, reg);
+	pmg = FIELD_GET(MPAMF_ESR_PMG, reg);
+	ris = FIELD_GET(MPAMF_ESR_PMG, reg);

MPAMF_ESR_RIS?

Yup, thanks for catching that!


James