Re: [PATCH v2 5/8] drivers/perf: hisi: Update DDRC PMU for programable counter

Hi Mark，

在 2021/2/3 21:23, Mark Rutland 写道:

On Wed, Feb 03, 2021 at 03:51:05PM +0800, Shaokun Zhang wrote:

quoted

DDRC PMU's events are useful for performance profiling, but the events
are limited and counters are fixed. On HiSilicon Hip09 platform, PMU
counters are the programmable and more events are supported. Let's
add the DDRC PMU v2 driver.

quoted

 static struct attribute *hisi_ddrc_pmu_v1_events_attr[] = {
 	HISI_PMU_EVENT_ATTR(flux_wr,		0x00),
 	HISI_PMU_EVENT_ATTR(flux_rd,		0x01),

@@ -240,6 +370,18 @@ static const struct attribute_group hisi_ddrc_pmu_v1_events_group = {
 	.attrs = hisi_ddrc_pmu_v1_events_attr,
 };
 
+static struct attribute *hisi_ddrc_pmu_v2_events_attr[] = {
+	HISI_PMU_EVENT_ATTR(clocks,		0x00),

Should that be 'cycles' ?

Yes, I will fix this.

quoted

+	HISI_PMU_EVENT_ATTR(flux_wr,		0x83),
+	HISI_PMU_EVENT_ATTR(flux_rd,		0x84),
+	NULL
+};

The commit message mentioned that v2 supports more events, but this only
adds three of them (and v2 listed eight distinct events).

Is there a rationale for only listing these events specifically?

We only put some events to calculate the bandwidth in this list and some
more events will be listed in JSON file which will be upstreamed later.
Because on HiSilicon Hip09 platform, it supports multi-chips and multi-dies
and each die has 4 or 6 DDRCs, if we lists more events in kernel driver,
it will list too many events in perf list and it is a little not friendly
to user.

Thanks,
Shaokun

Thanks,
Mark.
.

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