Hi Lorenzo,

Thanks a lot for your comments!

-----Original Message-----
From: Lorenzo Pieralisi <redacted>
Sent: 2019年6月29日 0:02
To: Z.q. Hou <zhiqiang.hou@nxp.com>
Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
[off-list ref]; catalin.marinas@arm.com; will.deacon@arm.com;
Mingkai Hu [off-list ref]; M.h. Lian [off-list ref];
Xiaowei Bao [off-list ref]
Subject: Re: [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for
MEM inbound transactions

On Fri, Apr 12, 2019 at 08:36:00AM +0000, Z.q. Hou wrote:

quoted

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The inbound windows have independent register set against outbound

windows.

quoted

This patch change the MEM inbound window to the first one.

You mean that windows 0 can be used as well as window 1 for inbound
windows so it is better to opt for window 0 for consistency ?

I mean the inbound windows and outbound windows are independent, they
have themselves' registers, and both serial number starts from 0:
Inbound windows: #0, #1, #2...
Outbound windows: #0, #1, #2... 

Thanks,
Zhiqiang

Lorenzo

quoted

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <redacted>
---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c

b/drivers/pci/controller/pcie-mobiveil.c
index df71c11b4810..e88afc792a5c 100644

--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c

@@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie

*pcie)

quoted

 			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));

 	/* memory inbound translation window */
-	program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE,

IB_WIN_SIZE);

quoted

+	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE,
+IB_WIN_SIZE);

 	/* Get the I/O and memory ranges from DT */
 	resource_list_for_each_entry(win, &pcie->resources) {
--
2.17.1

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