On 2013/10/17 23:27, Steven Rostedt wrote:

On Thu, 17 Oct 2013 22:40:32 +0800
Jiang Liu [off-list ref] wrote:

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You could make the code more concise by limiting your patching ability to
branch immediates. Then a nop is simply a branch to the next instruction (I
doubt any modern CPUs will choke on this, whereas the architecture requires
a NOP to take time).

I guess a NOP should be more effecient than a "B #4" on real CPUs:)

Well, I was actually questioning that. A NOP *has* to take time (the
architecture prevents implementations from discaring it) whereas a static,
unconditional branch will likely be discarded early on by CPUs with even
simple branch prediction logic.

I naively thought "NOP" is cheaper than a "B" :(
Will use a "B #1" to replace "NOP".

Really?? What's the purpose of a NOP then? It seems to me that an
architecture is broken if a NOP is slower than a static branch.

-- Steve

Hi Steve and Will,
	I have discussed this with one of our chip design members.
He thinks "NOP" should be better than "B #1" because jump instruction
is one of the most complex instructions for microarchitecture, which
may stall the pipeline. And NOP should be friendly enough for all
microarchitectures. So I will keep the "NOP" version.
Thanks!
Gerry