On 10/17/2013 05:39 PM, Will Deacon wrote:

On Wed, Oct 16, 2013 at 06:11:45PM +0100, Jiang Liu wrote:

quoted

On 10/16/2013 07:46 PM, Will Deacon wrote:

quoted

quoted

+	} else {
+		insn = aarch64_insn_gen_nop();

You could make the code more concise by limiting your patching ability to
branch immediates. Then a nop is simply a branch to the next instruction (I
doubt any modern CPUs will choke on this, whereas the architecture requires
a NOP to take time).

I guess a NOP should be more effecient than a "B #4" on real CPUs:)

Well, I was actually questioning that. A NOP *has* to take time (the
architecture prevents implementations from discaring it) whereas a static,
unconditional branch will likely be discarded early on by CPUs with even
simple branch prediction logic.

I naively thought "NOP" is cheaper than a "B" :(
Will use a "B #1" to replace "NOP".

Thanks!
Gerry

Will