[PATCH 09/12] ARM: OMAP2+: powerdomain: skip register reads for powerdomains known to be on

On Wed, 19 Dec 2012, Jon Hunter wrote:

My understanding is that for OMAP4 devices, the core power domain may
not be active the same time as the MPU power domain. The Cortex-A9 has
the ability to access some peripherals (such as timer, McBSP) via a
private bus that does not require the core domain to be active. This is
a difference from OMAP3 devices, where the core would always be on with
the MPU power domain.

You are absolutely right and I will drop that part from this patch.


- Paul