[PATCH 4/5] ARM: scu: Move register defines to header file

On Tue, Jan 25, 2011 at 06:06:27PM +0530, Santosh Shilimkar wrote:

Ok. I missed some information my last email.
The SCU power status programming is used to take CPU in/out
of coherency as an alternative to SMP bit. We don't
have an access to SMP bit on OMAP4. ARM has already
confirmed SCU programming is same as SMP bit enable/disable.

I don't know how safe is to use spin lock when one CPU is
goes out of coherency after programming the power state. The
spin lock release may not even be visible to other CPU.
The programming happens from IDLE or suspend where the

BTW, presumably we should be flushing the caches/tlbs before setting
the CPU power register to a non-normal setting?

I'll wait until there's more information available (such as an example
implementation.)