Thread (155 messages) 155 messages, 18 authors, 2010-03-11

USB mass storage and ARM cache coherency

From: benh@kernel.crashing.org (Benjamin Herrenschmidt)
Date: 2010-02-26 21:42:55
Also in: lkml

On Fri, 2010-02-26 at 16:25 +0000, Catalin Marinas wrote:
For mmap'ed pages (and present in the page cache), is it guaranteed that
the HCD driver won't write to it once it has been mapped into user
space? If that's the case, it may solve the problem by just reversing
the meaning of PG_arch_1 on ARM and assume that a newly allocated page
has dirty D-cache by default.
Well, I don't see why the HCD would write to it unless it's swapped out,
and thus unmapped or read() to or similar.
The filesystem layer does it only if it needs to touch the data written
by the block device (e.g. cramfs, jffs). Some block devices call
flush_dcache_page (like mmci.c) while some others don't (and those that
use DMA actually don't since the DMA API handles the flushing). 
Hrm, the DMA API certainly doesn't handle the I$/D$ coherency on
powerpc.. I'm afraid that whole cache handling stuff is totally
inconsistent since different archs have different expectations here.

Maybe we need to revisit things in that area, though it might require to
be done properly to have not one but two bits in struct page to
separately track the D$ and I$ state ...

Cheers,
Ben.
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