Thread (155 messages) 155 messages, 18 authors, 2010-03-11

USB mass storage and ARM cache coherency

From: oliver@neukum.org (Oliver Neukum)
Date: 2010-02-24 07:16:27
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Am Mittwoch, 24. Februar 2010 03:48:09 schrieb Benjamin Herrenschmidt:
On Fri, 2010-02-19 at 21:53 +0100, Oliver Neukum wrote:
quoted
Am Freitag, 19. Februar 2010 18:36:51 schrieb Catalin Marinas:
quoted
If a page is already mapped in user space, flush_dcache_page() on ARM
does the flushing rather than deferring it to update_mmu_cache(). The
PIO HCD drivers, however, don't call flush_dcache_page(). Is it possible
that the HCD could transfer data into a page cache page already mapped
in user space? My understanding is that the scenario above is possible.
Yes, video drivers do that. 
In which case it would be up to the video driver to call
flush_dcache_page() (though if it's v4l you are talking about, maybe it
might make sense to push it into the v4l layer itself).
I don't know. The issue seems quite complex. It would seem better to
centralize it as far as practical. Do you have a wrapper drivers could
call?

	Regards
		Oliver
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