On Wed, Mar 31, 2021 at 8:44 AM Guo Ren [off-list ref] wrote:

On Wed, Mar 31, 2021 at 12:18 PM Guo Ren [off-list ref] wrote:

quoted

On Tue, Mar 30, 2021 at 3:12 PM Arnd Bergmann [off-list ref] wrote:

quoted

On Tue, Mar 30, 2021 at 4:26 AM Guo Ren [off-list ref] wrote:

quoted

quoted

As I understand, this example must not cause a deadlock on
a compliant hardware implementation when the underlying memory
has RsrvEventual behavior, but could deadlock in case of
RsrvNonEventual

Thx for the nice explanation:
 - RsrvNonEventual - depends on software fall-back mechanisms, and
just I'm worried about.
 - RsrvEventual - HW would provide the eventual success guarantee.

In riscv-spec 8.3 Eventual Success of Store-Conditional Instructions

I found:
"As a consequence of the eventuality guarantee, if some harts in an
execution environment are
executing constrained LR/SC loops, and no other harts or devices in
the execution environment
execute an unconditional store or AMO to that reservation set, then at
least one hart will
eventually exit its constrained LR/SC loop. *** By contrast, if other
harts or devices continue to
write to that reservation set, it ***is not guaranteed*** that any
hart will exit its LR/SC loop.*** "

Seems RsrvEventual couldn't solve the code's problem I've mentioned.

Ok, got it.

        Arnd