Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
From: Peter Zijlstra <peterz@infradead.org>
Date: 2021-03-29 07:51:38
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linux-riscv, lkml
On Sat, Mar 27, 2021 at 06:06:38PM +0000, guoren@kernel.org wrote:
From: Guo Ren <redacted> Some architectures don't have sub-word swap atomic instruction, they only have the full word's one. The sub-word swap only improve the performance when: NR_CPUS < 16K * 0- 7: locked byte * 8: pending * 9-15: not used * 16-17: tail index * 18-31: tail cpu (+1) The 9-15 bits are wasted to use xchg16 in xchg_tail. Please let architecture select xchg16/xchg32 to implement xchg_tail.
So I really don't like this, this pushes complexity into the generic code for something that's really not needed. Lots of RISC already implement sub-word atomics using word ll/sc. Obviously they're not sharing code like they should be :/ See for example arch/mips/kernel/cmpxchg.c. Also, I really do think doing ticket locks first is a far more sensible step.