On Mon, Mar 29, 2021 at 7:26 PM Peter Zijlstra [off-list ref] wrote:

On Mon, Mar 29, 2021 at 07:19:29PM +0800, Guo Ren wrote:

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On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra [off-list ref] wrote:

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On Sat, Mar 27, 2021 at 06:06:38PM +0000, guoren@kernel.org wrote:

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From: Guo Ren <redacted>

Some architectures don't have sub-word swap atomic instruction,
they only have the full word's one.

The sub-word swap only improve the performance when:
NR_CPUS < 16K
 *  0- 7: locked byte
 *     8: pending
 *  9-15: not used
 * 16-17: tail index
 * 18-31: tail cpu (+1)

The 9-15 bits are wasted to use xchg16 in xchg_tail.

Please let architecture select xchg16/xchg32 to implement
xchg_tail.

So I really don't like this, this pushes complexity into the generic
code for something that's really not needed.

Lots of RISC already implement sub-word atomics using word ll/sc.
Obviously they're not sharing code like they should be :/ See for
example arch/mips/kernel/cmpxchg.c.

I see, we've done two versions of this:
 - Using cmpxchg codes from MIPS by Michael
 - Re-write with assembly codes by Guo

But using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.

What? -ENOPARSE

u32 a = 0x55aa66bb;
u16 *ptr = &a;

CPU0                       CPU1
=========             =========
xchg16(ptr, new)     while(1)
                                    WRITE_ONCE(*(ptr + 1), x);

When we use lr.w/sc.w implement xchg16, it'll cause CPU0 deadlock.

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Also, I really do think doing ticket locks first is a far more sensible
step.

NACK by Anup

Who's he when he's not sending NAKs ?

We've talked before:
https://lore.kernel.org/linux-riscv/CAAhSdy1JHLUFwu7RuCaQ+RUWRBks2KsDva7EpRt8--4ZfofSUQ@mail.gmail.com/T/#t (local)

-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/