Thread (111 messages) 111 messages, 27 authors, 10h ago

Re: [PATCH 2/3] vmsplice: make vmsplice a trivial wrapper for preadv2/pwritev2

From: Florian Weimer <hidden>
Date: 2026-06-05 09:33:01
Also in: linux-fsdevel, linux-mm, linux-patches, lkml, netdev

* Linus Torvalds:
On Thu, 4 Jun 2026 at 14:32, David Laight [off-list ref] wrote:
quoted
I think riscv might sign extend 32bit values in 64bit registers.
x86 and arm both zero extend.
That's different.

x86 really doesn't *care*. If the caller zero-extends or leaves high
bits set randomly, according to the x86 ABI that's perfectly fine: the
callee will only care about the low 32 bits. So the high bits are
simply not relevant for the ABI.
Please note that Clang does not implement the x86-64 ABI and requires
zero extension.  We see increasing problems from that, now that we have
more C code calling Rust code.  (The other direction is generally fine.)
Unfortunately, it's difficult to fix in LLVM.

In the original x86-64 psABI, this was left unspecified by omission
except for the special case of _Bool.  However, Clang/LLVM gets the
_Bool case wrong as well, so it's not just a matter of an unclear
specification.

This isn't really specific to x86-64.  _Bool is simply not part of the
ABI that is stable across compilers, a bit like bitfields in structs
passed by value.

Thanks,
Florian
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