This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.

Signed-off-by: Tim Whisonant <redacted>
Signed-off-by: Enno Luebbers <redacted>
Signed-off-by: Shiva Rao <redacted>
Signed-off-by: Christopher Rauer <redacted>
Signed-off-by: Kang Luwei <redacted>
Signed-off-by: Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Signed-off-by: Wu Hao <redacted>
----
v3: rename driver to dfl-fpga-fme-mgr
    implemented status callback for fpga manager
    rebased due to fpga api changes
---
 .../ABI/testing/sysfs-platform-fpga-dfl-fme-mgr    |   8 +
 drivers/fpga/Kconfig                               |   6 +
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/fpga-dfl-fme-mgr.c                    | 318 +++++++++++++++++++++
 drivers/fpga/fpga-dfl.h                            |  39 ++-
 5 files changed, 371 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme-mgr
 create mode 100644 drivers/fpga/fpga-dfl-fme-mgr.c

diff --git a/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme-mgr b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme-mgr
new file mode 100644
index 0000000..2d4f917
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-platform-fpga-dfl-fme-mgr

@@ -0,0 +1,8 @@
+What:          /sys/bus/platform/devices/fpga-dfl-fme-mgr.0/interface_id
+Date:          November 2017
+KernelVersion:  4.15
+Contact:       Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+Description:   Read-only. It returns interface id of partial reconfiguration
+               hardware. Userspace could use this information to check if
+               current hardware is compatible with given image before FPGA
+               programming.

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 57da904..0171ecb 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig

@@ -150,6 +150,12 @@ config FPGA_DFL_FME
          FPGA platform level management features. There shall be 1 FME
          per DFL based FPGA device.

+config FPGA_DFL_FME_MGR
+       tristate "FPGA DFL FME Manager Driver"
+       depends on FPGA_DFL_FME
+       help
+         Say Y to enable FPGA Manager driver for FPGA Management Engine.
+
 config INTEL_FPGA_DFL_PCI
        tristate "Intel FPGA DFL PCIe Device Driver"
        depends on PCI && FPGA_DFL

diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index cc75bb3..6378580 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile

@@ -31,6 +31,7 @@ obj-$(CONFIG_OF_FPGA_REGION)          += of-fpga-region.o
 # FPGA Device Feature List Support
 obj-$(CONFIG_FPGA_DFL)                 += fpga-dfl.o
 obj-$(CONFIG_FPGA_DFL_FME)             += fpga-dfl-fme.o
+obj-$(CONFIG_FPGA_DFL_FME_MGR)         += fpga-dfl-fme-mgr.o

 fpga-dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o

diff --git a/drivers/fpga/fpga-dfl-fme-mgr.c b/drivers/fpga/fpga-dfl-fme-mgr.c
new file mode 100644
index 0000000..70356ce
--- /dev/null
+++ b/drivers/fpga/fpga-dfl-fme-mgr.c

@@ -0,0 +1,318 @@
+/*
+ * FPGA Manager Driver for FPGA Management Engine (FME)
+ *
+ * Copyright (C) 2017 Intel Corporation, Inc.
+ *
+ * Authors:
+ *   Kang Luwei <luwei.kang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Xiao Guangrong <guangrong.xiao-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
+ *   Wu Hao <hao.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Joseph Grecco <joe.grecco-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Enno Luebbers <enno.luebbers-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Tim Whisonant <tim.whisonant-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Ananda Ravuri <ananda.ravuri-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Christopher Rauer <christopher.rauer-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *   Henry Mitchel <henry.mitchel-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
+ *
+ * This work is licensed under the terms of the GNU GPL version 2.
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <linux/module.h>
+#include <linux/iopoll.h>
+#include <linux/fpga/fpga-mgr.h>
+
+#include "fpga-dfl.h"
+#include "dfl-fme.h"
+
+#define PR_WAIT_TIMEOUT   8000000
+#define PR_HOST_STATUS_IDLE    0
+
+struct fme_mgr_priv {
+       void __iomem *ioaddr;
+       u64 pr_error;
+};
+
+static ssize_t interface_id_show(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+       struct fpga_manager *mgr = dev_get_drvdata(dev);
+       struct fme_mgr_priv *priv = mgr->priv;
+       u64 intfc_id_l, intfc_id_h;
+
+       intfc_id_l = readq(priv->ioaddr + FME_PR_INTFC_ID_L);
+       intfc_id_h = readq(priv->ioaddr + FME_PR_INTFC_ID_H);
+
+       return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n",
+                       (unsigned long long)intfc_id_h,
+                       (unsigned long long)intfc_id_l);
+}
+static DEVICE_ATTR_RO(interface_id);
+
+static const struct attribute *fme_mgr_attrs[] = {
+       &dev_attr_interface_id.attr,
+       NULL,
+};
+
+static u64 pr_error_to_mgr_status(u64 err)
+{
+       u64 status = 0;
+
+       if (err & FME_PR_ERR_OPERATION_ERR)
+               status |= FPGA_MGR_STATUS_OPERATION_ERR;
+       if (err & FME_PR_ERR_CRC_ERR)
+               status |= FPGA_MGR_STATUS_CRC_ERR;
+       if (err & FME_PR_ERR_INCOMPATIBLE_BS)
+               status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
+       if (err & FME_PR_ERR_PROTOCOL_ERR)
+               status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
+       if (err & FME_PR_ERR_FIFO_OVERFLOW)
+               status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
+
+       return status;
+}
+
+static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
+{
+       u64 pr_status, pr_error;
+
+       pr_status = readq(fme_pr + FME_PR_STS);
+       if (!(pr_status & FME_PR_STS_PR_STS))
+               return 0;
+
+       pr_error = readq(fme_pr + FME_PR_ERR);
+       writeq(pr_error, fme_pr + FME_PR_ERR);
+
+       return pr_error;
+}
+
+static int fme_mgr_write_init(struct fpga_manager *mgr,
+                             struct fpga_image_info *info,
+                             const char *buf, size_t count)
+{
+       struct device *dev = &mgr->dev;
+       struct fme_mgr_priv *priv = mgr->priv;
+       void __iomem *fme_pr = priv->ioaddr;
+       u64 pr_ctrl, pr_status;
+
+       if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+               dev_err(dev, "only support partial reconfiguration.\n");

+               return -ETIMEDOUT;
+       }
+
+       dev_dbg(dev, "PR operation complete, checking status\n");
+       priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
+       if (priv->pr_error) {
+               dev_dbg(dev, "PR error detected %llx\n",
+                       (unsigned long long)priv->pr_error);
+               return -EIO;
+       }
+
+       dev_dbg(dev, "PR done successfully\n");
+
+       return 0;
+}
+
+static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr)
+{
+       return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static u64 fme_mgr_status(struct fpga_manager *mgr)
+{
+       struct fme_mgr_priv *priv = mgr->priv;
+
+       return pr_error_to_mgr_status(priv->pr_error);
+}
+
+static const struct fpga_manager_ops fme_mgr_ops = {
+       .write_init = fme_mgr_write_init,
+       .write = fme_mgr_write,
+       .write_complete = fme_mgr_write_complete,
+       .state = fme_mgr_state,
+       .status = fme_mgr_status,
+};
+
+static int fme_mgr_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct fme_mgr_priv *priv;
+       struct fpga_manager *mgr;
+       struct resource *res;
+       int ret;
+
+       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+       if (!priv)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       priv->ioaddr = devm_ioremap(dev, res->start, resource_size(res));
+       if (IS_ERR(priv->ioaddr))
+               return PTR_ERR(priv->ioaddr);
+
+       ret = sysfs_create_files(&pdev->dev.kobj, fme_mgr_attrs);
+       if (ret)
+               return ret;
+
+       mgr = devm_kzalloc(dev, sizeof(*mgr), GFP_KERNEL);
+       if (!mgr)
+               goto sysfs_remove_exit;
+
+       mgr->name = "DFL FPGA Manager";
+       mgr->mops = &fme_mgr_ops;
+       mgr->priv = priv;
+       mgr->parent = dev;
+       platform_set_drvdata(pdev, mgr);
+
+       ret = fpga_mgr_register(mgr);
+       if (ret) {
+               dev_err(dev, "unable to register FPGA manager\n");
+               goto sysfs_remove_exit;
+       }
+
+       return 0;
+
+sysfs_remove_exit:
+       sysfs_remove_files(&pdev->dev.kobj, fme_mgr_attrs);
+       return ret;
+}
+
+static int fme_mgr_remove(struct platform_device *pdev)
+{
+       struct fpga_manager *mgr = platform_get_drvdata(pdev);
+
+       fpga_mgr_unregister(mgr);
+       sysfs_remove_files(&pdev->dev.kobj, fme_mgr_attrs);
+
+       return 0;
+}
+
+static struct platform_driver fme_mgr_driver = {
+       .driver = {
+               .name    = FPGA_DFL_FME_MGR,
+       },
+       .probe   = fme_mgr_probe,
+       .remove  = fme_mgr_remove,
+};
+
+module_platform_driver(fme_mgr_driver);
+
+MODULE_DESCRIPTION("FPGA Manager for FPGA Management Engine");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:fpga-dfl-fme-mgr");

diff --git a/drivers/fpga/fpga-dfl.h b/drivers/fpga/fpga-dfl.h
index e5a1094..d45eb82 100644
--- a/drivers/fpga/fpga-dfl.h
+++ b/drivers/fpga/fpga-dfl.h

@@ -130,7 +130,44 @@

 /* FME Partial Reconfiguration Sub Feature Register Set */
 #define FME_PR_DFH             DFH
-#define FME_PR_SIZE            DFH_SIZE
+#define FME_PR_CTRL            0x8
+#define FME_PR_STS             0x10
+#define FME_PR_DATA            0x18
+#define FME_PR_ERR             0x20
+#define FME_PR_INTFC_ID_H      0xA8
+#define FME_PR_INTFC_ID_L      0xB0
+#define FME_PR_SIZE            0xB8
+
+/* FME PR Control Register Bitfield */
+#define FME_PR_CTRL_PR_RST     BIT(0)  /* Reset PR engine */
+#define FME_PR_CTRL_PR_RSTACK  BIT(4)  /* Ack for PR engine reset */
+#define FME_PR_CTRL_PR_RGN_ID  GENMASK_ULL(9, 7)       /* PR Region ID */
+#define FME_PR_CTRL_PR_START   BIT(12) /* Start to request for PR service */
+#define FME_PR_CTRL_PR_COMPLETE        BIT(13) /* PR data push complete notification */
+
+/* FME PR Status Register Bitfield */
+/* Number of available entries in HW queue inside the PR engine. */
+#define FME_PR_STS_PR_CREDIT   GENMASK_ULL(8, 0)
+#define FME_PR_STS_PR_STS      BIT(16) /* PR operation status */
+#define FME_PR_STS_PR_STS_IDLE 0
+#define FME_PR_STS_PR_CTRLR_STS        GENMASK_ULL(22, 20)     /* Controller status */
+#define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24)     /* PR host status */
+
+/* FME PR Data Register Bitfield */
+/* PR data from the raw-binary file. */
+#define FME_PR_DATA_PR_DATA_RAW        GENMASK_ULL(32, 0)
+
+/* FME PR Error Register */
+/* Previous PR Operation errors detected. */
+#define FME_PR_ERR_OPERATION_ERR       BIT(0)
+/* CRC error detected. */
+#define FME_PR_ERR_CRC_ERR             BIT(1)
+/* Incompatible PR bitstream detected. */
+#define FME_PR_ERR_INCOMPATIBLE_BS     BIT(2)
+/* PR data push protocol violated. */
+#define FME_PR_ERR_PROTOCOL_ERR                BIT(3)
+/* PR data fifo overflow error detected */
+#define FME_PR_ERR_FIFO_OVERFLOW       BIT(4)

 /* FME HSSI Sub Feature Register Set */
 #define FME_HSSI_DFH           DFH