diff --git a/drivers/dpll/dpllsim/dpll.c b/drivers/dpll/dpllsim/dpll.c
index 3caccd38a7e74a..77e7ae994bf104 100644
--- a/drivers/dpll/dpllsim/dpll.c
+++ b/drivers/dpll/dpllsim/dpll.c
@@ -12,6 +12,11 @@
#include "dpllsim.h"
+#define DPLLSIM_PHASE_ADJUST_GRAN 100 /* ps */
+/* Largest multiple of the granularity, so the range ends are settable */
+#define DPLLSIM_PHASE_ADJUST_MAX \
+ (S32_MAX - S32_MAX % DPLLSIM_PHASE_ADJUST_GRAN)
+
static struct dpll_pin_frequency dpllsim_freq_1pps[] = {
DPLL_PIN_FREQUENCY_RANGE(1, 1),
};@@ -159,6 +164,33 @@ static int dpllsim_pin_prio_set(const struct dpll_pin *pin, void *pin_priv,
return 0;
}
+static int dpllsim_pin_phase_adjust_get(const struct dpll_pin *pin,
+ void *pin_priv,
+ const struct dpll_device *dpll,
+ void *dpll_priv, s32 *phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct dpllsim_pin *sim_pin = pin_priv;
+
+ guard(mutex)(&sim_pin->dev->lock);
+ *phase_adjust = sim_pin->phase_adjust;
+ return 0;
+}
+
+static int dpllsim_pin_phase_adjust_set(const struct dpll_pin *pin,
+ void *pin_priv,
+ const struct dpll_device *dpll,
+ void *dpll_priv,
+ const s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct dpllsim_pin *sim_pin = pin_priv;
+
+ guard(mutex)(&sim_pin->dev->lock);
+ sim_pin->phase_adjust = phase_adjust;
+ return 0;
+}
+
static const struct dpll_pin_ops dpllsim_input_pin_ops = {
.frequency_get = dpllsim_pin_frequency_get,
.frequency_set = dpllsim_pin_frequency_set,@@ -167,6 +199,8 @@ static const struct dpll_pin_ops dpllsim_input_pin_ops = {
.state_on_dpll_set = dpllsim_pin_state_set,
.prio_get = dpllsim_pin_prio_get,
.prio_set = dpllsim_pin_prio_set,
+ .phase_adjust_get = dpllsim_pin_phase_adjust_get,
+ .phase_adjust_set = dpllsim_pin_phase_adjust_set,
};
static const struct dpll_pin_ops dpllsim_output_pin_ops = {@@ -174,6 +208,8 @@ static const struct dpll_pin_ops dpllsim_output_pin_ops = {
.frequency_set = dpllsim_pin_frequency_set,
.direction_get = dpllsim_pin_direction_get,
.state_on_dpll_get = dpllsim_pin_state_get,
+ .phase_adjust_get = dpllsim_pin_phase_adjust_get,
+ .phase_adjust_set = dpllsim_pin_phase_adjust_set,
};
static const struct dpll_pin_ops *@@ -189,6 +225,9 @@ static void dpllsim_pin_props(struct dpllsim_pin *pin,
{
prop->type = pin->type;
prop->board_label = config_item_name(&pin->item);
+ prop->phase_range.min = -DPLLSIM_PHASE_ADJUST_MAX;
+ prop->phase_range.max = DPLLSIM_PHASE_ADJUST_MAX;
+ prop->phase_gran = DPLLSIM_PHASE_ADJUST_GRAN;
switch (pin->type) {
case DPLL_PIN_TYPE_GNSS:@@ -250,6 +289,7 @@ static void dpllsim_pin_reset(struct dpllsim_pin *pin)
{
pin->ops = dpllsim_pin_select_ops(pin);
pin->state = DPLL_PIN_STATE_DISCONNECTED;
+ pin->phase_adjust = 0;
}
/* Build sim->pins in registration order, the order the pins were created */diff --git a/drivers/dpll/dpllsim/dpllsim.h b/drivers/dpll/dpllsim/dpllsim.h
index f59447d26a8668..886ac27f5f92d6 100644
--- a/drivers/dpll/dpllsim/dpllsim.h
+++ b/drivers/dpll/dpllsim/dpllsim.h
@@ -43,6 +43,7 @@ struct dpllsim_pin {
/* Simulated state, guarded by dev->lock */
enum dpll_pin_state state;
+ s32 phase_adjust;
};
struct dpllsim_dev {--
2.56.0