Re: [PATCH v2 04/10] dt-bindings: net: pcs: add rockchip,rk3568-xpcs binding
From: Krzysztof Kozlowski <krzk@kernel.org>
Date: 2026-08-05 07:29:56
Also in:
linux-arm-kernel, linux-devicetree, linux-phy, linux-renesas-soc, linux-rockchip, lkml
On Sat, Aug 01, 2026 at 10:22:28PM +0800, Coia Prant wrote:
Add device tree binding documentation for the Synopsys DesignWare XPCS integrated on the Rockchip RK3568 SoC. The XPCS is accessed over the APB3 bus and internally connected to a Naneng Combo SerDes PHY. It supports 1000BASE-X, SGMII, and QSGMII modes, with four MII ports. The binding describes: - Required properties: compatible, reg, clocks, clock-names - Optional properties: phys, phy-names, power-domains - pcs-mii sub-nodes for each MII port (reg 0..3)
Irrelevant paragraph. We can read the diff. Drop. A nit, subject: drop second/last, redundant "binding". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23
quoted hunk ↗ jump to hunk
Signed-off-by: Coia Prant <redacted> --- .../bindings/net/pcs/rockchip-dwxpcs.yaml | 127 ++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yamldiff --git a/Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml b/Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml new file mode 100644 index 0000000000000..3e3f3a388d822 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/rockchip-dwxpcs.yaml@@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/rockchip-dwxpcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS + +maintainers: + - Coia Prant <coiaprant@gmail.com> + +description: | + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physical + Coding Sublayer (XPCS). + The PCS provides an interface between the Media Access Control (MAC) + and the Physical Medium Attachment (PMA) sublayer through a Media + Independent Interface (GMII). + + The XPCS is accessed over the APB3 bus and internally connected to a + Naneng Combo SerDes PHY. + It supports 1000BASE-X, SGMII and QSGMII modes. + + The block contains four MII ports (pcs-mii@0..3) that can be + individually enabled and routed to one of the Ethernet GMAC controllers + via the pcs-handle property in the MAC device tree node. + +properties: + compatible: + const: rockchip,rk3568-xpcs + + '#address-cells': + const: 1 + + '#size-cells': + const: 0
reg is always the second property. Also, use consistent style of quotes.
+ + reg: + description: | + Base address and size of the XPCS register space mapped over the + APB3 bus.
Drop description, redundant.
+ maxItems: 1 + + clocks: + description: | + Clock sources for the XPCS: + - csr: APB3 bus interface clock (clk_csr_i), required for register + access. + - eee: EEE clock (clk_eee_i), required for Energy Efficient + Ethernet (EEE) operation. + minItems: 2 + maxItems: 2
No, instead list items with description.
+ + clock-names: + items: + - const: csr + - const: eee + + phys: + description: |
Do not need '|' unless you need to preserve formatting.
+ The phandle of SerDes PHY (Naneng Combo PHY) that provides + the serial lanes for 1000BASE-X / SGMII / QSGMII. + The SerDes must be powered on and initialised before any XPCS + register access. + maxItems: 1 + + phy-names: + const: serdes + + power-domains: + description: | + Power domain for the XPCS.
Drop sentence and |
+ On RK3568 this is typically the PD_PIPE power domain, which also + supplies the SerDes PHY. + maxItems: 1 + +patternProperties: + "^pcs-mii@[0-3]$":
Why `git grep pcs-mii@` gives me no results? Are you doing this similarly to existing devices or is this quite different device than every other hardware?
+ type: object + description: |
Same here
+ One of the four MII ports of the XPCS. + The port number is specified by the reg property (0..3).
Drop sentence, redundant. Schema tells that.
+ The port is linked to an Ethernet MAC controller via the + pcs-handle property in the MAC's device tree node. + + properties: + reg: + minimum: 0 + maximum: 3 + description: |
As well
+ MII port number of PCS. + + status: true
Nope, do you see anywhere code like this?
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3568-cru.h>
+ #include <dt-bindings/power/rk3568-power.h>
+ #include <dt-bindings/phy/phy.h>
+
+ pcs@fda00000 {
+ compatible = "rockchip,rk3568-xpcs";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfda00000 0x200000>;
+ clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
+ clock-names = "csr", "eee";
+ phys = <&combphy2 PHY_TYPE_SGMII>;
+ phy-names = "serdes";
+ power-domains = <&power RK3568_PD_PIPE>;
+
+ pcs-mii@0 {
+ reg = <0>;
+ };
+ };
--
2.47.3