[PATCH rdma-next 15/15] RDMA/mlx5: Enforce relaxed ordering when HW requires it
From: Michael Gur <hidden>
Date: 2026-07-26 09:31:22
Also in:
linux-rdma, lkml
Subsystem:
infiniband subsystem, mellanox mlx5 ib driver, the rest · Maintainers:
Jason Gunthorpe, Leon Romanovsky, Linus Torvalds
Add relaxed ordering validation (relaxed or unordered) to enforce no strong ordered mkeys are created when the HW disallows it. Reject MR registrations that do not request IB_ACCESS_RELAXED_ORDERING or IB_ACCESS_UNORDERED. Invoke the validator from all user-facing MR registration paths, including the Device Memory path (mlx5_ib_reg_dm_mr). Reviewed-by: Yishai Hadas <yishaih@nvidia.com> Signed-off-by: Michael Gur <redacted> --- drivers/infiniband/hw/mlx5/mr.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 31879c0ecfb3..5a7bec0d7edd 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c@@ -84,6 +84,16 @@ static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr, MLX5_SET64(mkc, mkc, start_addr, start_addr); } +static int validate_ordering_access(struct mlx5_ib_dev *dev, int acc) +{ + /* If HW disallows Strong Ordered writes, RO/UNORDERED must be set */ + if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro_only)) { + if (!(acc & (IB_ACCESS_RELAXED_ORDERING | IB_ACCESS_UNORDERED))) + return -EOPNOTSUPP; + } + return 0; +} + static void assign_mkey_variant(struct mlx5_ib_dev *dev, u32 *mkey, u32 *in) { u8 key = atomic_inc_return(&dev->mkey_var);
@@ -679,8 +689,13 @@ struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, { struct mlx5_ib_dm *mdm = to_mdm(dm); struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev; + struct mlx5_ib_dev *ib_dev = to_mdev(dm->device); u64 start_addr = mdm->dev_addr + attr->offset; - int mode; + int mode, err; + + err = validate_ordering_access(ib_dev, attr->access_flags); + if (err) + return ERR_PTR(err); switch (mdm->type) { case MLX5_IB_UAPI_DM_TYPE_MEMIC:
@@ -843,6 +858,10 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, mlx5_ib_dbg(dev, "start 0x%llx, iova 0x%llx, length 0x%llx, access_flags 0x%x\n", start, iova, length, access_flags); + err = validate_ordering_access(dev, access_flags); + if (err) + return ERR_PTR(err); + err = mlx5r_umr_resource_init(dev); if (err) return ERR_PTR(err);
@@ -1034,6 +1053,10 @@ struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 offset, "offset 0x%llx, virt_addr 0x%llx, length 0x%llx, fd %d, access_flags 0x%x, mlx5_access_flags 0x%x\n", offset, virt_addr, length, fd, access_flags, mlx5_access_flags); + err = validate_ordering_access(dev, access_flags); + if (err) + return ERR_PTR(err); + /* dmabuf requires xlt update via umr to work. */ if (!mlx5r_umr_can_load_pas(dev, length)) return ERR_PTR(-EINVAL);
@@ -1167,6 +1190,10 @@ struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, if (!(flags & IB_MR_REREG_PD)) new_pd = ib_mr->pd; + err = validate_ordering_access(dev, new_access_flags); + if (err) + return ERR_PTR(err); + if (mr->is_odp_implicit && !(flags & IB_MR_REREG_TRANS)) { if (!(new_access_flags & IB_ACCESS_ON_DEMAND)) return ERR_PTR(-EOPNOTSUPP);
--
2.52.0