On hardware that restricts strong-ordering access for memory
registrations, set relaxed ordering on MW mkeys.
Without this change, MW allocation mkey creation fails on such HW.
Enabling RO implicitly for users in this case is acceptable since all
users share the same memory registration restriction, so any MR bound to
this MW is guaranteed to have relaxed ordering as well.
Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Michael Gur <redacted>
---
drivers/infiniband/hw/mlx5/mr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 683099333563..29a9da5c6dca 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -1822,6 +1822,9 @@ int mlx5_ib_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
MLX5_SET(mkc, mkc, en_rinval, !!((ibmw->type == IB_MW_TYPE_2)));
MLX5_SET(mkc, mkc, qpn, 0xffffff);
+ if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro_only))
+ mlx5_core_mkey_set_relaxed_ordering(dev->mdev, mkc);
+
err = mlx5_ib_create_mkey(dev, &mw->mmkey, in, inlen);
if (err)
goto free;
--
2.52.0