[PATCH rdma-next 06/15] net/mlx5: Add IFC bits for new ordering caps
From: Michael Gur <hidden>
Date: 2026-07-26 09:30:42
Also in:
linux-rdma, lkml
Subsystem:
mellanox mlx5 ib driver, mellanox mlx5 core vpi driver, the rest · Maintainers:
Leon Romanovsky, Saeed Mahameed, Tariq Toukan, Mark Bloch, Linus Torvalds
Add new HCA capability bits: - mkc_order_read_after_write - mkc_order_write_after_write_ro_only Add new mkey context field: - order_read_after_write (2-bit) These fields enable a new level of memory access order relaxation, allowing read-after-write reordering and allow to expose an indication that devices don't support strict ordering of memory access. Reviewed-by: Yishai Hadas <yishaih@nvidia.com> Signed-off-by: Michael Gur <redacted> --- include/linux/mlx5/mlx5_ifc.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 0593913fd25f..160dbbc5d338 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h@@ -2003,7 +2003,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 roce_rw_supported[0x1]; u8 log_max_current_uc_list_wr_supported[0x1]; u8 log_max_stride_sz_rq[0x5]; - u8 reserved_at_3a8[0x3]; + u8 mkc_order_read_after_write[0x1]; + u8 mkc_order_write_after_write_ro_only[0x1]; + u8 reserved_at_3aa[0x1]; u8 log_min_stride_sz_rq[0x5]; u8 reserved_at_3b0[0x3]; u8 log_max_stride_sz_sq[0x5];
@@ -4518,6 +4520,10 @@ enum { MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, }; +enum { + MLX5_MKC_ORDER_READ_AFTER_WRITE_RO = 1, +}; + struct mlx5_ifc_mkc_bits { u8 reserved_at_0[0x1]; u8 free[0x1];
@@ -4565,7 +4571,9 @@ struct mlx5_ifc_mkc_bits { u8 translations_octword_size[0x20]; - u8 reserved_at_1c0[0x19]; + u8 reserved_at_1c0[0x16]; + u8 order_read_after_write[0x2]; + u8 reserved_at_1d8[0x1]; u8 pci_relaxed_ordered_read[0x1]; u8 log_page_size[0x6];
--
2.52.0